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Accelerating Vitis HLS Development with the AMD Ross Agentic AI Assistant
This course introduces the AMD Ross™ agentic AI assistant for Vitis™ high-level synthesis (HLS) and demonstrates how AI-assisted workflows can improve productivity throughout the HLS development process. Participants ...

Adaptive SoCs for System Architects
This course provides system architects with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC and Versal™ adaptive SoC devices.The emphasis is on:Utilizing power management strategies ef...

Classroom - Advanced Versal Adaptive SoC AI Engine - PLC2 version
With the Versal Adaptive Compute Acceleration Platform (ACAP) family XILINX introduces versions of these devices with a special feature, the AI Engine. The AI Engine offers high performance, low latency capabilities f...

Classroom - Advanced VHDL (PLC2 version)
In recent years, EDA tool vendors like AMD and Aldec have improved their VHDL support not only in simulation, but also in synthesis. The tools enhancements partially cover latest VHDL-2019, as well as major improve...

Classroom - Advanced Vivado (PLC2 version)
The AMD Vivado™ design suite tool provides many features which offer valuable features for the experienced hardware designer. Extended tool features are needed for a higher productivity in the development process: the...

Classroom - Advanced Zynq UltraScale+ MPSoC for the Software Designer (PLC2 version)
This course explains the features of the CPUs in the processing system to effectively design embedded software for operating systems and complex applications.In systems deploying multiple independent processors in ope...

Classroom - Arm Cortex-A53/R5 for Zynq UltraScale+MPSoC (Doulos version)
This course covers the software aspects of designing with an Arm® Cortex®-A53 MPCore based device, highlighting the core architecture details and the Xilinx® Zynq® UltraScale+™ implementation choices.Topics include th...


Classroom - Compact Advanced VHDL Testbenches and Verification /OSVVM (PLC2 course)
Compact Advanced VHDL Testbenches and Verification /OSVVM (PLC2 course)

Classroom - Compact DSP Design for Versal Using Vitis Model Composer (PLC2 version)
With MATLAB™ and Simulink™, Vitis™ Model Composer offers several toolboxes for DSP development.The HDL toolbox is based on VHDL/Verilog code generation and the HLS toolbox the C/C++-based code generation using Vitis™ ...