| In recent years, EDA tool vendors like AMD and Aldec have improved their VHDL support not only in simulation, but also in synthesis. The tools enhancements partially cover latest VHDL-2019, as well as major improvements in long missing VHDL-2008 language constructs. As the time is right and tools are stable, it is time to summarize PLC2's knowledge on advanced VHDL coding techniques. The added »new features« support in writing more efficient test benches, allowing to use verification frameworks like OSVVM, UVVM or VUnit, but also in designing reusable synthesis components. A developer is now enabled to be as efficient in code as in graphical design. This brings back more control to the engineers. Further, this eases the use of version control tools like Git and teamwork. As another benefit, synthesis times can be drastically reduced, allowing more builds or tests per day. This course will discuss various topics of VHDL atop of a general understanding of VHDL. It will focus on using records to connect components in a design. Procedures will be used to manipulate record elements. Finally, mode views (a.k.a. interfaces), are used to describe per record element directions. Moreover, an introduction to OSVVM APIs will be given for basic logging/reporting and randomization. |
