Designing with the Versal Adaptive SoC: Design Methodology
Course Details
Length:
32 Hours
Number of Labs:
11
Number of Chapter:
24
Current Version:
2026.1
Number of Demos:
0
Overview
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and thermal solutions to enhance the performance of a design.
This course provides virtual access to a Versal VCK190 Evaluation Platform to complete one of the two board-based labs included in the course.
The emphasis of this course is on:
Demonstrating the embedded software development flow for Versal devices
Demonstrating the AI Engine development flow
Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems
Leveraging the Power Design Manager (PDM) tool for power estimation
Identifying Versal adaptive SoC power and thermal solutions
Enabling top-level RTL flows for Versal devices
Applying common timing closure techniques
Performing device configuration and debugging
Improving Versal adaptive SoC system performance
Performing system-level simulation
What's New:
System Integration and Validation Methodology module: Added information on optimizing PL performance through pipelining and floorplanning techniques
Segmented Configuration module: Added details on Segmented Configuration + DFX support for Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2
Added a new module on the Advanced Configuration Editor
System Simulation module: Introduced the AMD Vitis™ Hardware in the Loop (HIL) framework
All labs have been updated to the latest software versions
