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Designing FPGAs Using the Vivado Design Suite 3 - Virtual Board

Course Details
Length: 21 Hours
Number of Labs: 12
Number of Chapter: 23
Current Version: 2024.2
Number of Demos: 6

Overview

Learn how to effectively employ timing closure techniques.
This course includes:
  • Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
  • Showing optimum HDL coding techniques that help with design timing closure
  • Illustrating the advanced capabilities of the Vivado™ logic analyzer to debug a design
This course builds further on the previous Designing FPGAs Using the Vivado Design Suite courses.
This course also provides virtual access to a Zynq™ UltraScale+™ ZCU104 board to perform all sections of the labs that require a board.
CHAPTERS

UltraFast Design Methodology - Implementation

Timing Simulation

Baselining

Pipelining

Inference

I/O Timing Scenarios

System-Synchronous I/O Timing

Source-Synchronous I/O Timing

Timing Constraints Priority

Report Clock Interaction

Report Datasheet

QoR Reports Overview

Sampling and Capturing Data in Multiple Clock Domains (Virtual Board Access)

Clock Domain Crossing and Synchronization Circuits

Revision Control Systems in the Vivado Design Suite

Dynamic Power Estimation Using Vivado Report Power

Configuration Modes

Netlist Insertion Debug Probing Flow (Virtual Board Access)

JTAG to AXI Master Core

Debug Flow in an IP Integrator Block Design (Virtual Board Access)

Remote Debugging Using the Vivado Logic Analyzer (Virtual Board Access)

Design Analysis Using Tcl Commands

Designing FPGAs Using the Vivado Design Suite 3 Full Course Quiz

OTHER FORMATS

On Demand Trainings

Virtual Classroom

Live Classroom
  • USD Price = 399
Training Credit Price = 4 TC
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Questions?
Featured Board
Kintex UltraScale FPGA KCU105 Evaluation Kit
KCU105
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Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit
ZCU104
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