This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify your design under test (DUT) utilizing the new constructs available...
With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family -Adaptive Compute Acceleration Platform. The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity...
VHDL for Designers (Xilinx) prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essentia...
This course provides experience with using the Vitis™ Model Composer tool for model-based designs. The course provides experience with: Creating a model-based design using HDL, HLS, and AI Engine library blocks.
This course provides embedded system developers with skills in creating an embedded Linux system targeting AMD SoCs using the Yocto Project.Setting up the Yocto environment, fetching the repositories, configuring the ...
Provides experiences system architects with the knowledge on how to best architect a Zynq® System on a Chip (SoC) device project.This course covers:Identifying the features and benefits of the Zynq SoC architectureDes...
This course provides system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family.The emphasis is on:Utilizing power management strategies effectivelyLeveraging the platfo...
In this Free OnDemand curriculum you will learn how to migrate GPU‑accelerated applications from CUDA to AMD ROCm™ using HIP, by understanding RDNA™ architecture and SIMT execution, mapping CUDA to HIP, optimizing mem...
Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, ...
