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Classroom - Designing with the Ultrascale+ MPSoC (Doulos Version)
This five-day LIVE Online Training (LOT) course is structured to provide FPGA HW, SW and system architects with an overview of the capabilities and support for the Zynq UltraScale+ MPSoC family.
Designing with the UltraScale and UltraScale+ Architectures
This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regional ...
Virtual - Designing with the UltraScale and UltraScale+ Architectures
This course introduces the AMD UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regio...
Virtual - Designing with the Ultrascale+ MPSoC (Doulos version)
This four-day LIVE Online Training (LOT) course is structured to provide FPGA HW, SW and system architects with an overview of the capabilities and support for the Zynq UltraScale+ MPSoC family.