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Classroom - Compact VHDL for Synthesis (PLC2 version)

This workshop will teach the synthesis relevant aspects of the VHDL hardware description language based on the IEEE Std. 1076-2008 language revision.The theoretical knowledge will be deepened with selected examples and labs on PC.

3/16/2026 - 3/18/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Freiburg - PLC2 Office
Address : Hugstmattweg 30,Freiburg,GERMANY
6/15/2026 - 6/17/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Frankfurt - TBD PLC2 Venue
Address : TBD,Frankfurt,GERMANY
9/21/2026 - 9/23/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Stuttgart - TBD PLC2 Venue
Address : TBD,Stuttgart,GERMANY
11/23/2026 - 11/25/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Munchen - TBD PLC2 Venue
Address : TBD,Munchen,GERMANY
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