This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective.
The emphasis is on:
Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
Reviewing the various power domains and their control structure
Illustrating the processing system (PS) and programmable logic (PL)connectivity
Utilizing QEMU to emulate hardware behavior
8/5/2025 - 8/6/2025 Time Zone : (GMT+09:00) Osaka, Sapporo, Tokyo Seats Remaining : 7 Venue : Online HDLAB Address : 3-18-14 Shin-Yokohama, Kohoku-ku,Sumisei Shin-Yokohama Daini Bldg. 4F.,Yokohama,JAPAN
