This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective.
The emphasis is on:
Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
Reviewing the various power domains and their control structure
Illustrating the processing system (PS) and programmable logic (PL)connectivity
Utilizing QEMU to emulate hardware behavior
7/12/2026 - 7/14/2026 Time Zone : (GMT+02:00) Israel ,Jerusalem Seats Remaining : 16 Venue : ISR, Petah-Tikva - Logtel Headquarters Address : 32 Shacham St, Ramat-Siv Industrial Park,Petah-Tikva,ISRAEL
