Utilizing the Vivado™ IP integrator to create a sub-system
Performing power analysis and optimization to improve the power efficiency of a design
Reviewing and analyzing timing reports for a design
This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course
7/2/2026 - 7/3/2026 Time Zone : (GMT-06:00) Central Time (US & Canada) Seats Remaining : 6 Venue : USA, MN, Orono - Morgan A.P.S., Inc. Address : 2500 Shadywood Rd.,Suite 535,Orono,MN,USA
10/6/2026 - 10/7/2026 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : NLD - Heesch - CoreVision Headquarters Address : Cereslaan 24,Heesch,NETHERLANDS
10/19/2026 - 10/20/2026 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 10 Venue : AUT Vienna - So-Logic Office Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
