Customer Training Center

Sign In
Xilinx is now part ofAMDUpdated Privacy Policy

Classroom - Designing FPGAs Using the Vivado Design Suite 1

This course offers introductory training on the AMD Vivado™ Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.

The course provides experience with:
  • Creating a Vivado Design Suite project with source files
  • Simulating a design
  • Performing pin assignments
  • Applying basic timing constraints
  • Synthesizing and implementing
  • Debugging a design
  • Generating and downloading a bitstream onto a demo board

7/9/2026 - 10/9/2026
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
9/29/2026 - 9/30/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 5
Venue : NLD - Heesch - CoreVision Headquarters
Address : Cereslaan 24,Heesch,NETHERLANDS
1/7/2027 - 1/8/2027
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
Add to Cart
Show Detailed Course Description
Questions?