Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components.
This course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics Hyper Lynx. Other topics include managing PCB effects and on-chip termination.
9/22/2025 - 9/24/2025 Time Zone : (GMT+08:00) Kuala Lumpur, Singapore Seats Remaining : 8 Venue : Techsource Systems - Singapore Address : 10 Ubi Crescent #06-48 Ubi Techpark Lobby C,Singapore,SINGAPORE
