This two-part free workshop explores the power and capabilities of High-Level Synthesis (AMD Vitis HLS) to dramatically accelerate embedded software to hardware speeds.
It will provide an overview of the HLS design process, explain the component development flow, demonstrate how to explore design alternatives using directives and introduce interfacing with the accelerated hardware block.
Further details on optimizing performance by optimizing dataflows and pipelining will be provided.
4/23/2026 - 4/24/2026 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 5000 Venue : Online - Doulos Ltd Address :
4/23/2026 - 4/24/2026 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 5000 Venue : Online - Doulos Inc Address :
