The focus of this workshop is on learning the key features and architecture of the AMD Spartan UltraScale+ FPGA, including its advanced I/O, high-speed transceivers, substantial built-in and external memory, PCIe Gen4 connectivity, and modern security. Recognize how these features provide a versatile, cost-optimized, and power-efficient platform for diverse applications.
The emphasis of this course is on:
Describing the key features and fundamental blocks of the Spartan UltraScale+ FPGA architecture
Describing Spartan UltraScale+ clock structure and layout
Utilizing the advanced I/O capabilities for various connectivity needs
Utilizing the Spartan UltraScale+ DSP resources
Identifying the high-speed transceivers for use in applications such as PCIe Gen4
5/20/2026 - 5/20/2026 Time Zone : (GMT-05:00) Eastern Time (US & Canada) Seats Remaining : 200 Venue : Online - BLT Address : www.bltinc.com
