Following an initial overview, the course takes a closer look at the Spartan™ UltraScale+™ clocking architecture and its management concepts. You will learn how to make the most of memory resources using different types such as CLB-RAM, Block RAM, UltraRAM, and FIFOs. This section explains the key functional blocks of this architecture, including Configurable Logic Blocks (CLBs), I/O features, and DSP resources, and how to use them effectively. This training also provides essential knowledge on how to migrate from the Spartan™-7 series to the Spartan™ UltraScale™ architecture, with particular emphasis on clocking resources and structure, which is a vital aspect of any FPGA design.
To top the content off, dedicated hardware resources such as Gigabit Transceivers and PCIe® will briefly be introduced. In addition, the course explains suitable coding techniques to ensure efficient synthesis results tailored to the target device’s resources.
3/18/2026 - 3/20/2026 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Stuttgart - TBD PLC2 Venue Address : TBD,Stuttgart,GERMANY
7/22/2026 - 7/24/2026 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Frankfurt - TBD PLC2 Venue Address : TBD,Frankfurt,GERMANY
11/11/2026 - 11/13/2026 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Freiburg - PLC2 Office Address : Hugstmattweg 30,Freiburg,GERMANY
