This course provides a thorough introduction to high-level synthesis (HLS) using the AMD Vitis™ Unified IDE. The focus of this course is on: Converting C/C++ designs into RTL implementations.
7/21/2026 - 10/22/2026 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 10 Venue : AUT Vienna - So-Logic Office Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
3/1/2027 - 9/7/2027 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 10 Venue : AUT Vienna - So-Logic Office Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
