This course provides a thorough introduction to high-level synthesis (HLS) using the AMD Vitis™ Unified IDE. The focus of this course is on: Converting C/C++ designs into RTL implementations.
6/22/2026 - 11/22/2026 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 0 Venue : AUT Vienna - So-Logic On-Line Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
