This course covers the AMD Versal™ architecture and illustrates the tool flow for developing HLS and AI Engine components as well as integrating an entire system project to design an embedded heterogeneous system.
4/12/2027 - 9/12/2027 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 10 Venue : AUT Vienna - So-Logic Office Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
