This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the AMD Versal™ adaptive SoC architecture.
5/3/2027 - 11/9/2027
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
