This course provides a system-level understanding of AMD Versal™ adaptive SoC memory interfaces. Memory controller architecture, IP generation, simulation, and implementation are covered.
9/23/2026 - 9/24/2026 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 10 Venue : AUT Vienna - So-Logic Office Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
