Vitis™ Model Composer provides the HLS blockset in the Xilinx toolbox. This enables you to transform your algorithmic specifications to production-quality IP implementations using automatic optimizations and leveraging the high-level synthesis technology of Vitis HLS. Using the IP integrator in Vivado, you can then integrate the IP into a platform that, for example, may include a Zynq® device, DDR3 DRAM, and a software stack running on an Arm® processor.
The HLS library in the Xilinx Toolbox provides optimized blocks for use within the Simulink environment. These include basic functional blocks for expressing algorithms like Math, Linear Algebra, Logic, and Bit-wise operations and others.
In this webinar, you will learn about the Model-Based Design workflow using HLS blockset of Model Composer, how to setup the Simulink model using blocks from HLS library and do automatic code generation.
Highlights
- Design Flows using Model Composer
- Creating Model Composer design with HLS blocks
- Working with Data Types
- Importing C/C++ Code as Custom Blocks
- Generating Outputs
- Simulating and Verifying the Design.
11/17/2025 - 11/17/2025 Time Zone : (GMT+08:00) Kuala Lumpur, Singapore Seats Remaining : 100 Venue : Online - TechSource Systems Address : Live Online
11/24/2025 - 11/24/2025 Time Zone : (GMT+08:00) Kuala Lumpur, Singapore Seats Remaining : 100 Venue : Online - TechSource Systems Address : Live Online
