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Classroom - Versal Adopter Series: All thing PL, Enhanced DSP58, Etc. (Technically Speaking)

This is Session 6 in the Versal Adopter Series -
Topics Include:
  • Utilizing and optimizing programmable logic
  • CLB structure
  • Memory resources, LUT-RAM, BRAM, URAM
  • Using and optimizing DSP58 slices
  • Pros and cons of HDL coding versus HLS
  • HDL coding techniques and recommendations
  • Synthesis and compiler optimization
  • Synchronous design techniques
  • Clocking techniques and recommendations
  • Managing control sets
  • Interfacing to AIE
  • Timing closure techniques for PL fabric

12/2/2025 - 12/2/2025
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 6
Venue : USA, CA, Irvine - Avnet Office
Address : 220 Commerce #100,Irvine,CA,USA
12/3/2025 - 12/3/2025
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 5
Venue : Avnet San Diego
Address : 13500 Evening Creek Dr. N,Suite 400,San Diego,CA,USA
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