During the typical design cycle, a solution for a task or even a complete system may be drafted in an abstract behavioral model, quite often in higher level languages like C/C++ .The Vitis(TM) High Level Synthesis helps to derive an optimized RTL IP out of such descriptions and can boost design productivity with this approach. In this Online Live training, we will cover the tool chain operation, which has seen some updates in handling and content in the latest VitisTM Unified IDE releases.
The benefits in this approach, like e re-using the C/C++ level tests for the synthesized RTL code yield quite some benefits when comparing traditional HDL designs, still it is mandatory to understand the principles to generate a suitable solution. Therefore, we will discuss quite a range of topics: - The VitisTM HLS flow - Updates and new features - Interface definitions - Task-level parallelism - Functions and loops - Optimization strategies - Libraries
11/26/2025 - 11/26/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 149 Venue : Online - PLC2 Address :
