We will derive a complete data driven design from start in AMD VivadoTM, where the general architecture is visible already to guide into the common features. The sessions touch further on the traditional embedded design flow but extends into software defined hardware accelerators. All of this is created and driven by the AMD VitisTM Unified IDE well into final validation in emulation or running hardware.
You will be walked through: - Adaptive SoC Technology Primer - The Core Project Flow from Vivado to Vitis unified IDE - Multicore Design - Conceptual of Software Defined Accelerators - System Integration and Validation
9/30/2025 - 9/30/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 136 Venue : Online - PLC2 Address :
