Classroom - Design Compendium with Verilog for AMD devices (So-Logic)

"Basic FPGA Tutorial" is a document made for beginners who are entering the FPGA world. This tutorial explains, step by step, the procedure of designing a simple digital system using Verilog language and AMD Xilinx Vivado Design Suite.
In the "Basic FPGA Tutorial", a PWM signal modulated using the sine wave with two different frequencies (1 Hz and 3.5Hz) will be created. Frequency that will be chosen depends on the position of the two-state on-board switch.

7/6/2026 - 11/27/2026
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
4/12/2027 - 10/15/2027
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA