This workshop provides an overview of implementation strategies and tooling for processing the massive computation of deep neural networks on programmable devices. The AMD adaptive SoCs are a suitable target for these approaches where, dependent on the device family, parts of the processing can be mapped to FPGA fabric (programmable logic implementation), to specific vector processing elements (AI Engines in Versal™) or the hard IP CPUs these devices offer.
9/15/2025 - 9/17/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Munchen - TBD PLC2 Venue Address : TBD,Munchen,GERMANY
11/19/2025 - 11/21/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Stuttgart - TBD PLC2 Venue Address : TBD,Stuttgart,GERMANY
