This course covers the AMD Versal™ architecture and illustrates the tool flow for developing HLS and AI Engine components as well as integrating an entire system project to design an embedded heterogeneous system using the v++ tools and AMD Vitis™ Unified IDE.
The emphasis of this course is on:
Describing an embedded heterogeneous system design
Illustrating the AMD Versal adaptive SoC architecture, NoC, and AI Engine
Describing an AMD Versal design tool flow
Developing HLS and AIE components using the AMD Vitis tool
Utilizing the v++ command line tools for component compilation, linking, and packaging to run emulation.
Demonstrating the system design flow for a heterogeneous embedded system using the AMD Vitis Unified IDE
10/7/2025 - 10/9/2025 Time Zone : (GMT-05:00) Eastern Time (US & Canada) Seats Remaining : 20 Venue : Online - BLT Address : www.bltinc.com
6/2/2026 - 6/4/2026 Time Zone : (GMT-05:00) Eastern Time (US & Canada) Seats Remaining : 20 Venue : Online - BLT Address : www.bltinc.com
