In this seminar we would explore the AMD Versal™ adaptive SoC heterogeneous architecture and concentrate in three important aspects of the architecture (i) the programmable network on chip (NoC), (ii) the memory interfaces and (iii) tools and techniques available to debug AMD Versal devices.
9/10/2025 - 9/10/2025 Time Zone : (GMT+00:00) GMT Seats Remaining : 16 Venue : ESP, Madrid - Universidad Autonoma de Madrid Address : Fco Tomas y Valiente 11,School of Engineering,Madrid,SPAIN
