This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement a Versal™ device PCIe® solution in custom applications to improve time to market. At the beginning of this class, an introduction to the vocabulary and the transmission protocol are given, along with details on the structure and content of data packets. This is a solid foundation for building your own application. After that, the main aspects of this training class are simulation and implementation of a provided example design. This way, the learning experience is the most realistic while allowing one to easily put the theory into reality. The interface between the core blocks and the user application is especially emphasized. The available signals and their correct usage are discussed in the necessary detail. This course discusses both, the PL and the CPM PCIe® solutions. During the training, the target technology will be the Versal™ AI Core seriesVCK190 evaluation board. The working principles and the protocol information, however, are equally valid for other Versal™ hardware, too.
10/15/2025 - 10/16/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Stuttgart - TBD PLC2 Venue Address : TBD,Stuttgart,GERMANY
