This five-days workshop includes teaching DSP and acceleration development methods for both generic FPGAs and Versal™ adaptive SoC technologies using the AMD Vitis™ Tools Model Composer, which needs to be used with MATLAB™ and Simulink™.
Different toolboxes are provided with Vitis™ Model Composer: HDL Toolbox, HLS toolbox, and AIE toolbox. DSP algorithms can be implemented in different ways or in a combination with these methods. Hardware developers in particular benefit from the HDL toolbox, image processing is best supported in particular by the HLS toolbox and the AI Engine kernels can in turn be optimally developed with the AIE toolbox with Versal™.
Processor-supported hardware acceleration methods are also simplified with these methods.
The workshop is recommended for algorithm developers, hardware developers, and software developers.
9/1/2025 - 9/5/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Freiburg - PLC2 Office Address : Hugstmattweg 30,Freiburg,GERMANY
12/15/2025 - 12/19/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Berlin - TBD PLC2 Venue Address : TBD,Berlin,GERMANY
