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Virtual - Compact DSP Design for FPGAs Using Vitis Model Composer (PLC2 version)

With MATLAB™ and Simulink™, Vitis™ Model Composer offers several toolboxes for DSP development.
The HDL toolbox is based on VHDL/Verilog code generation and the HLS tool box the C/C++-based code generation using Vitis™ HLS. The methods of the DSP-based design model are explained and applied in accompanying exercises with data type management, MATLAB™ simulation, HDL-simulation, and C-simulation, and code generation that offers resource and performance optimizations much more easily than the classic HDL/Verilog design draft.

Model-based abstraction facilitates faster design drafts, simulation is performed under MATLAB™, and optimization is simplified with AMD-optimized tool boxes and MATLAB™ libraries enabling system simulations incorporating the DSP algorithms implemented for the AMD platform. The capabilities of a flexible data type management with integer, fixed point, or floating point and with support of quantization and necessarily conversion will be described and demonstrated.

2/9/2026 - 2/11/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : Online - PLC2
Address :
6/22/2026 - 6/24/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : Online - PLC2
Address :
9/21/2026 - 9/23/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : Online - PLC2
Address :
12/14/2026 - 12/16/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : Online - PLC2
Address :
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