The continuously rising demand for highly complex programmable logic in combination with ever-increasing clock rates hold challenges for the users. SystemVerilog (IEEE1800) as the successor of the already very popular Verilog Hardware Description Language (HDL) brings all features to describe logic in a scalable and reusable fashion, extending the design methods seamlessly into verification. It has become a major tool of choice in FGPA and ASIC designs, supported by virtually all EDA vendor tools.
In this workshop, SystemVerilog is presented using a set of modern and powerful HDL-based design techniques that support a high design quality for any physical target. The examples and labs during the sessions aim at FPGA fabric as a demonstration vehicle for language features, while SystemVerilog is even more established in ASIC designs. The course presents the SystemVerilog concepts and core syntax and fosters insight into its successful usage. Also, attendees are introduced to basic modular design elements as well as principal verification approaches set within the hardware programming language.
7/28/2025 - 7/30/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Freiburg - PLC2 Office Address : Hugstmattweg 30,Freiburg,GERMANY
10/29/2025 - 10/31/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Munchen - TBD PLC2 Venue Address : TBD,Munchen,GERMANY
