VHDL is a strongly typed hardware description language that prohibits typical programming mistakes in the coding phase. Usually, VHDL is used on the Register Transfer Level (RTL) to design digital circuits of any complexity. Apart from the language constructs for synthesis, VHDL offers a wide range of functionality to describe complex verification models. Thus, it is possible to verify digital designs from simple gate-up to complicated System on Chip (SoC) before going to lab tests. With recourse to already well-known VHDL language features, this workshop will deepen the knowledge in VHDL and enable the attendee to create simulations with the VHDL test bench concept. The taught language constructs are based on the IEEE Std. 1076- 2008 language revision.
9/18/2025 - 9/19/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
11/6/2025 - 11/7/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
