Programmable logic devices like FPGAs have been established in daily life. They can be found in mobile phones, IoT devices, cars, or cloud data centers. Their area of operation is as broad as their size. FPGAs are used as, but are not limited to protocol adapters, signal converters, or accelerators for video, radar, and sensor data processing. The design of digital circuits on this scale needs a powerful hardware description language which offers different levels of abstraction, so an engineer can create a digital hardware design in a quick and effective way. VHDL fulfills these requirements.
VHDL is a strongly typed hardware description language that prohibits typical programming mistakes in the coding phase. Usually, VHDL is used on the Register Transfer Level (RTL) to design digital circuits of any complexity. Apart from the language constructs for synthesis, VHDL offers a wide range of functionality to describe complex verification models. Thus, it is possible to verify digital designs from simple gate-up to complicated System on Chip (SoC)before going to lab tests. This workshop will teach the synthesis of relevant aspects of the VHDL hardware description language based on the IEEE Std.1076-2008 language revision.
9/15/2025 - 9/17/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
11/3/2025 - 11/5/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
