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Classroom - Compact Timing Constraints and Analysis (PLC2 version)

The main pillars are aunified and scalable database allowing great cross-probing possibilities and aunique test environment for a shortened learning curve. In addition, increasedadherence to industry standards such as AMBA™ AXI4, IP-XACT (for metadata forself-developed IP cells), Tool command Language (Tcl), Synopsys DesignConstraints (SDC), etc. allows easy scalability and simplified automation ofthe development process. Vivado™ is conceptually designed in a way to deal withall aspects (logic, SW, I/O, mixed signal, etc.) of programmable technology andthis is for designs of a complexity of up to 100M ASIC gates.

This class gives a detailed discussion of the creation of XDC (AMD DesignConstraints) and the static timing analysis. On top, proper usage of FPGAresources is discussed along with how the unified Vivado™ design database canbe used efficiently for e.g., analysis purposes.

11/19/2025 - 11/21/2025
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 9
Venue : DEU, Munchen - TBD PLC2 Venue
Address : TBD,Munchen,GERMANY
2/11/2026 - 2/13/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Freiburg - PLC2 Office
Address : Hugstmattweg 30,Freiburg,GERMANY
6/24/2026 - 6/26/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Frankfurt - TBD PLC2 Venue
Address : TBD,Frankfurt,GERMANY
9/23/2026 - 9/25/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Stuttgart - TBD PLC2 Venue
Address : TBD,Stuttgart,GERMANY
11/18/2026 - 11/20/2026
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Munchen - TBD PLC2 Venue
Address : TBD,Munchen,GERMANY
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