This comprehensive course is a thorough introduction to SystemVerilog constructs for design and verification, it is a combination of the instructional material found in Designing with SystemVerilog and Verification with SystemVerilog. This class addresses writing RTL code using the new constructs available in SystemVerilog as well as test benches to verify your design under test (DUT). New data types, structs, unions, arrays, procedural blocks, and re-usable tasks, functions, and packages, are all covered in the designing phase of the course. Object-oriented modeling, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered in the verification phase. The information gained can be applied to any digital design and verification flow. This course combines insightful lectures with practical lab exercises to reinforce key concepts. In this three-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop and verify RTL designs.
10/14/2025 - 10/16/2025 Time Zone : (GMT-05:00) Eastern Time (US & Canada) Seats Remaining : 19 Venue : Online - BLT Address : www.bltinc.com
