The Xilinx Versal ACAP platform is multi-featured, offering unprecedented system level performance and integration. This informative workshop (delivered in 2half day sessions) is a comprehensive and practical introduction to the features and capabilities. We’ll first cover the broader Versal ACAP device. We’ll then focus on a practical example, optimizing a given application for the AI Engine resources.
Versal ACAP: Structural Overview – Big picture overview, processing engines, connections and capabilities
Intro to AI Engines – Scalar and vector processing unit, SIMD data-path, multi-kernel control and communication
PS Overview – Introduce the A72 and R5Fprocessors, MPSoC migration, the role of the PMU, device boot, etc.
PL Fabric – The traditional FPGA fabric, encompassing enhanced layout, clocking, and slice capabilities
NoC Resources – Overview for Versal ACAP communication backplane, data-transfer, DDR controller
EnhancedDSP58 – New features, layout and operational modes for PL fabric-based DSP building blocks
AIE Vector Datatypes – Declaring vector datatypes required for the high-performance SIMD data-paths
Intrinsic(s)Coding – Introduction to proprietary syntax for maximizing AI engine vector processing
FIR Filter Coding for AIE – A step-by-step working example for 1GHz+ FIR filter targeting AI engine
10/23/2025 - 10/24/2025 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 30000 Venue : Online - Doulos Inc Address :
11/20/2025 - 11/21/2025 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 3000 Venue : Online - Doulos Inc Address :
