This course provides a thorough introduction to the Vitis™ High-LevelSynthesis(HLS) tool.
The focus is on:
Covering synthesis strategies and features
Applying different optimization techniques
Improving throughput, area, interface creation, latency, test bench coding, and coding tips
Utilizing the Vitis HLS tool to optimize code for high-speed performance in an embedded environment
Downloading for in-circuit validation
10/5/2026 - 10/5/2026 Time Zone : (GMT+01:00) Brussels, Copenhagen, Madrid, Paris Seats Remaining : 16 Venue : ESP, Madrid - Universidad Autonoma de Madrid Address : Fco Tomas y Valiente 11,School of Engineering,Madrid,SPAIN
