This 3-day coursewill enable the software developer to get the best possible start on softwaredevelopment for the Versal ACAP family. This first explains the Versal ACAParchitecture and the unified Vitis Software Development tool with toolchain andmethods for the embedded design using the processors and toolchains forhardware acceleration using DSP engines, AI engines or adaptable engines in theprogrammable logic. Symmetric and asymmetric OS support, Open-source Linuxbuilds using Yocto and/or PetaLinux, FreeRTOS usage for the real-timeprocessing unit, Hypervisor support and at least mechanisms of bootconfigurations are shown and elaborated with lab exercises. Debugging in simulation, emulation and hardware debugging - various methods areintegral part of the Vitis tool. While multiple processors in the Versalarchitecture are often not running simultaneously in full performance mode, thepower management of resources is software programmable and so enables powerreduction in the runtime system. The management of boot images and boot loadersis also covered in the course.
8/25/2025 - 8/27/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
10/7/2025 - 10/9/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
