This 3-day course will enable the software developer to get the best possible start on software development for the Versal ACAP family. This first explains the Versal ACAP architecture and the unified Vitis Software Development tool with toolchain and methods for the embedded design using the processors and toolchains for hardware acceleration using DSP engines, AI engines or adaptable engines in the programmable logic. Symmetric and asymmetric OS support, Open-source Linuxbuilds using Yocto and/or PetaLinux, FreeRTOS usage for the real-time processing unit, Hypervisor support and at least mechanisms of boot configurations are shown and elaborated with lab exercises. Debugging in simulation, emulation and hardware debugging - various methods are integral part of the Vitis tool. While multiple processors in the Versal architecture are often not running simultaneously in full performance mode, the power management of resources is software programmable and so enables power reduction in the runtime system. The management of boot images and boot loaders is also covered in the course.
8/25/2025 - 8/27/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Freiburg - PLC2 Office Address : Hugstmattweg 30,Freiburg,GERMANY
10/7/2025 - 10/9/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Berlin - TBD PLC2 Venue Address : TBD,Berlin,GERMANY
