To overcomebottlenecks due to sequential processing in embedded systems FPGAs providemassive parallelism and application fitted data path. Xilinx supports suchheterogenous FPGA and CPU designs with the Vitis Unified Software Platform. Itallows projects for low level hardware drivers to be setup in one toolchainwith the data path projects that use high-level programming languages, e.g.OpenCL API for offloading functionality from CPU to FPGA kernels. This program gets the software developer started on the Vitis Unified SoftwarePlatform by introducing the Zynq SoC and MPSoC architectures. Softwaredevelopment knowledge for the standalone platform is provided to cover thebasic operation and low level services. Application development on the OS levelis combined with insight into driver development. On this platform all is setfor development, debug, and profiling of C/C++ and RTL applications targetingdata center (DC) and embedded (Edge) e.g. on the XILINX ALVEO acceleratorboard. Optimization topics and best practices will be provided all along.
8/25/2025 - 8/29/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
11/10/2025 - 11/14/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
