Sequential processing or data path speed is a bottleneck in manyhigh-end systems based on CPUs whereas FPGAs provide massive parallel dataprocessing along with optimized data path. A system with CPU and FPGAcombination would be an ideal solution by utilizing best of both worlds. ButFPGA development is more complex and often hard to achieve time-to-marketrequirements. Xilinx developed a hard- and software-based ecosystem to utilizeFPGAs as an application specific processing element along with CPU. Xilinx’ newunified software environment, called VITIS, offers the capabilities totranslate CPU code into such FPGA kernels. With these techniques FPGA baseddevelopment is streamlined by staying in high level programming languages andusing OpenCL API for application offloading and data path acceleration. In this course, you will learn how to develop, debug and profile new orexisting C/C++ and RTL applications with VITIS targeting both data center (DC)and embedded applications. You will also learn how to run designs on the XILINXALVEO accelerator board.
8/18/2025 - 8/20/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
11/3/2025 - 11/5/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
