Sequential processing or data path speed is a bottleneck in many high-end systems based on CPUs whereas FPGAs provide massive parallel data processing along with optimized data path. A system with CPU and FPGA combination would be an ideal solution by utilizing best of both worlds. But FPGA development is more complex and often hard to achieve time-to-market requirements. Xilinx developed a hard- and software-based ecosystem to utilize FPGAs as an application specific processing element along with CPU. Xilinx’ new unified software environment, called VITIS, offers the capabilities to translate CPU code into such FPGA kernels. With these techniques FPGA based development is streamlined by staying in high level programming languages and using OpenCL API for application offloading and data path acceleration. In this course, you will learn how to develop, debug and profile new or existing C/C++ and RTL applications with VITIS targeting both data center (DC) and embedded applications. You will also learn how to run designs on the XILINX ALVEO accelerator board.
8/18/2025 - 8/20/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Freiburg - PLC2 Office Address : Hugstmattweg 30,Freiburg,GERMANY
11/3/2025 - 11/5/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Frankfurt - TBD PLC2 Venue Address : TBD,Frankfurt,GERMANY
