SLVR - Designing with the Versal Adaptive SoC: Memory Interfaces
Course Details
Length:
19 Hours
Number of Labs:
7
Number of Chapter:
14
Current Version:
2025.1
Number of Demos:
0
Overview
This course provides a system-level understanding of AMD Versal™ adaptive SoC memory interfaces. Memory controller architecture, IP generation, simulation, and implementation are covered. Additional information on PCB design issues is also covered.
The focus is on:
Constructing a system using Versal adaptive SoC external memory interfaces by:
Selecting the appropriate IP for an application
Configuring the memory controller IPs
Using the memory controllers in test benches and applications
Simulating and implementing the memory controller IPs
Exploring traffic pattern generation
Performance tuning for the hardened DDRMC
Accessing the appropriate reference material for board design issues involving signal integrity, the power supply, reference clocking, and trace design
What,s New:
New DDR5/LPDDR5 module with DDRMC5 content added
New labs for DDRMC5 interface generation and simulation
All labs have been updated to the latest software versions
