SLVR - Designing with the Versal Adaptive SoC: Design Methodology
Course Details
Length:
32 Hours
Number of Labs:
11
Number of Chapter:
23
Current Version:
2025.2
Number of Demos:
0
Overview
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and thermal solutions to enhance the performance of a design.
The emphasis of this course is on:
Demonstrating the embedded software development flow for Versal devices
Demonstrating the AI Engine development flow
Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems
Leveraging the Power Design Manager (PDM) tool for power estimation
Identifying Versal adaptive SoC power and thermal solutions
Enabling top-level RTL flows for Versal devices
Applying common timing closure techniques
Performing device configuration and debugging
Improving Versal adaptive SoC system performance
Performing system-level simulation
What's New:
Added information on techniques for reducing clock skew in AMD Versal devices within the Versal Timing Closure Techniques module
Added information on SLR crossing report within the Optimizing SLR Crossings in SSI Technology module
Added new labs: Linux Application Development using the Embedded Development Framework (EDF) & Segmented Configuration for AMD Versal devices
All labs have been updated to the latest software versions
