PLT - Designing with the Versal Adaptive SoC: Quick Start
Course Details
Length:
10 Hours
Number of Labs:
4
Number of Chapter:
9
Current Version:
2026.1
Number of Demos:
0
Overview
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge of embedded software development and application partitioning. Also learn how to perform system migration to the Versal architecture.
The emphasis of this course is on:
Reviewing the architecture of the Versal adaptive SoC
Describing the different compute resources available in the Versal architecture
Demonstrating the embedded software development flow for Versal devices
Describing the architectures of the network on chip (NoC) and AI Engine
Explaining application partitioning based on the models of computation
Comparing various functional blocks of the Versal devices to previous-generation devices
What,s New:
Design Tool Flow module: Introduced the Vitis™ AI development flow and the Neural Processing Unit (NPU)
NoC Introduction and Concepts module: Introduced the latest Vivado™ Design Suite features for NoC development
System Migration module: Added information on device family-specific connectivity options across the Versal portfolio
All labs have been updated to the latest software versions
