This course covers the AMD Versal™ architecture and illustrates the tool flow for developing HLS and AI Engine components as well as integrating an entire system project when designing an embedded heterogeneous system using the v++ tools and AMD Vitis™ Unified IDE.
The emphasis of this course is on:
Describing an embedded heterogeneous system design
Illustrating the AMD Versal adaptive SoC architecture, NoC, and AI Engine
Describing an AMD Versal design tool flow
Developing HLS and AIE components using the AMD Vitis tool
Utilizing the v++ command line tools for component compilation, linking, and packaging to run emulation
Demonstrating the system design flow for a heterogeneous embedded system using the AMD Vitis Unified IDE
What's New:
Vitis HLS: Methodology and Optimization Techniques module: Added information on the HLS performance pragmas
Embedded Heterogeneous System Design Flow module: Added information on Vitis Functional Simulation and Vitis Subsystem Simulation
All labs have been updated to the latest software versions
