PLT - Designing with the Versal Adaptive SoC: Architecture
Course Details
Length:
21 Hours
Number of Labs:
8
Number of Chapter:
19
Current Version:
2024.2
Number of Demos:
0
Overview
Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as the programmable logic, high-speed I/O, clocking, processing system, AI Engines, and the programmable network on chip (NoC). Also learn how to use leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application.
The emphasis of this course is on:
Reviewing the architecture of the Versal adaptive SoC
Describing the different compute resources available in the Versal architecture
Describing the architectures of the network on chip (NoC) and AI Engine
Outlining the memory solutions and programming interfaces available in the Versal adaptive SoC
Identifying the PCI Express® and serial transceiver solutions available in the Versal adaptive SoC
What's New:
Added Versal RF series details in the Introduction module
Introduced the Advanced Flow for Versal implementation and the modular NoC flow in the Design Tool Flow module
Introduced new open early access segmented configuration feature in the Boot and Configuration module
Added modular NoC flow for RTL users in the NoC Introduction and Concepts module
Added new GT flow information in the Serial Transceivers module
Added a lab on the GT Wizard Subsystem flow
All labs have been updated to the latest software versions
