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Platinum Academy - Team (5 Users)
PLT - High-Level Synthesis with the Vitis Unified IDE
PLT - High-Level Synthesis with the Vitis Unified IDE
Course Details
Length:
29 Hours
Number of Labs:
13
Number of Chapter:
24
Current Version:
2024.2
Number of Demos:
0
Overview
This course provides a thorough introduction to high-level synthesis (HLS) using the AMD Vitis™ Unified IDE.
The focus of this course is on:
Converting C/C++ designs into RTL implementations
Learning the HLS component development flow
Creating I/O interfaces for designs
Applying different optimization techniques to designs
Improving throughput, area, latency, and logic by using different HLS pragmas/directives
Exporting IP that can be used with the Vivado™ IP catalog
Migrating designs from the classic Vitis HLS tool to the Vitis Unified IDE
What,s New:
Vitis HLS Libraries module: Added information on new featured libraries: Direct I/O, Fence, and DSP Intrinsics
All labs have been updated to the latest software versions
CHAPTERS
Introduction to High-Level Synthesis
HLS Component Development Flow
Abstract Parallel Programming Model for HLS
Design Exploration with Directives
HLS Component Development Using the Command Line
Introduction to Vitis HLS Design Methodology
Introduction to I/O Interfaces
Block-Level Protocols
Port-Level I/O Protocols
AXI Adapter Interface Protocols
Vitis HLS Code Analyzer
Optimizing for Performance: PIPELINE
Optimizing for Performance - DATAFLOW
Optimizing for Throughput
Optimizing for Latency Default Behavior
Optimizing for Latency - Reducing Latency
Optimizing for Area and Logic
Optimizing AXI System Performance
Vitis HLS Libraries
Vitis HLS Libraries: Arbitrary Precision Data Types
Using Pointers in Vitis HLS
HLS Component Design Flow - System Integration
Migrating to the Vitis Unified IDE - HLS Component
High-Level Synthesis with the Vitis Unified IDE Full Course Quiz
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