PLT - Zynq UltraScale+ MPSoC for the Hardware Designer

Course Details

Length: 22 Hours

Number of Labs: 7

Number of Chapter: 12

Current Version: 2024.2

Number of Demos: 1

Overview

This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective.

The emphasis is on:

Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
Reviewing the various power domains and their control structure
Illustrating the processing system (PS) and programmable logic (PL) connectivity
Utilizing QEMU to emulate hardware behavior

What,s New:

All labs have been updated to the latest software versions

CHAPTERS