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PLT - UltraFast Design Methodology

Course Details
Length: 20 Hours
Number of Labs: 8
Number of Chapter: 26
Current Version: 2024.2
Number of Demos: 2

Overview

Learn how to improve design speed and reliability by using the UltraFast™ Design Methodology and the Vivado™ Design Suite.
The focus is on:
  • Optimizing system reset design and synchronization circuits
  • Employing best practice HDL coding techniques
  • Applying appropriate timing closure techniques
  • Reviewing an UltraFast Design Methodology case study
What,s New:
All labs have been updated to the latest software versions.
CHAPTERS

UltraFast Design Methodology - Introduction

UltraFast Design Methodology - Board and Device Planning

AMD Vivado™ Design Suite IO Pin Planning

Power Estimation Using XPE

UltraFast Design Methodology - Design Creation

RTL Development

Resets

Pipelining

Synchronous Design Techniques

Getting Started with Vivado IP Integrator

Designing IP Subsystems Using Vivado IP Integrator: Introduction

Creating and Packaging Custom IP Introduction

Revision Control Systems in the Vivado Design Suite Introduction

UltraFast Design Methodology - Implementation

Incremental Compile Flow Introduction

UltraFast Design Methodology - Timing Closure

Introduction to AMD Vivado™ Reports

Baselining

Clock Domain Crossing and Synchronization Circuits Introduction

QoR Report

Timing Closure Using Physical Optimization Techniques

Power Management Techniques

Introduction to Floorplanning

Congestion

Vivado Design Suite Debug Methodology

UltraFast Design Methodology Full Course Quiz

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