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GLD - Designing FPGAs Using the Vivado Design Suite 3

Course Details
Length: 21 Hours
Number of Labs: 12
Number of Chapter: 23
Current Version: 2024.2
Number of Demos: 6

Overview

Learn how to effectively employ timing closure techniques.
This course includes:
  • Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
  • Showing optimum HDL coding techniques that help with design timing closure 
  • Illustrating the advanced capabilities of the Vivado™ logic analyzer to debug a design 
This course builds further on the previous Designing FPGAs Using the Vivado Design Suite courses. 
What,s New:
All labs have been updated to the latest software versions.
CHAPTERS

UltraFast Design Methodology - Implementation

Timing Simulation

Baselining

Pipelining

Inference

I/O Timing Scenarios

System-Synchronous I/O Timing

Source-Synchronous I/O Timing

Timing Constraints Priority

Report Clock Interaction

Report Datasheet

QoR Reports Overview

Sampling and Capturing Data in Multiple Clock Domains

Clock Domain Crossing and Synchronization Circuits

Revision Control Systems in the Vivado Design Suite

Dynamic Power Estimation Using Vivado Report Power

Configuration Modes

Netlist Insertion Debug Probing Flow

JTAG to AXI Master Core

Debug Flow in an IP Integrator Block Design

Remote Debugging Using the Vivado Logic Analyzer

Design Analysis Using Tcl Commands

Designing FPGAs Using the Vivado Design Suite 3 Full Course Quiz

OTHER FORMATS

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